1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device with a stress circuit and a stress voltage supplying method thereof which ensures the reliability of the device.
2. Description of the Related Art
With increasing integrations of semiconductor circuits, plane and vertical reductions in size are demanded. Cell structures for storing data are more scaled down and it is important to ensure their reliability because of the complicated processes required to produce minute patterns, sufficient step coverages, etc. In a semiconductor memory such as a dynamic RAM or a static RAM, a burn-in test is executed to examine the reliability of their internal circuits before or after a chip packaging process. To execute the burn-in test, a stress circuit for supplying a stress voltage is needed and this stress circuit is generally contained in test equipment. The burn-in test detects defects of memory cells in the chip or tests their integrity. Whether or not defects exist is determined by supplying an external supply voltage or higher voltage to each memory cell for a long time. Burn-in tests are used by all semiconductor manufacturing companies and constant efforts are made to develop effective burn-in tests. On the other hand, with the increasing integration of semiconductor memories, the test times therefore are increased in proportion thereto. In a 1M (Mega=2.sup.20 ) bit-class or less semiconductor memory device, test times do not effect the completion of the entire chip. However, in a 64M or 256M bit-class semiconductor memory device, the test time lengthens in accordance with an increase in the number of memory cells, causing an increase in chip manufacturing time. Consequently, the unit cost of production rises and it takes much time to manufacture products.
U.S. Pat. No. 5,119,337, issued Jun. 2, 1992 to Mitsuru Shimizu et al., entitled "SEMICONDUCTOR MEMORY DEVICE HAVING BURN-IN TEST FUNCTION" discloses techniques for improving the reliability of detecting defective memory cells by sufficiently raising a voltage level supplied to word lines during the burn-in test of dynamic RAMs in a package state. The techniques disclosed in the above patent have an advantage in that the test reliability is improved for the package state of the chip.
To test the chip in the package state, a method for applying stress to hundreds or thousands of packaged devices at high temperatures of about 125.degree. C. and high power voltages of 7 V or more has generally been used. In the method with such test conditions, micro defects such as defects in a gate oxide layer, capacitor oxide layer, metal bridge and poly bridge etc. can be screened. When the stress is applied, all the cells are scanned while writing data of a uniform pattern in the cell. The stress applied to each cell has a refresh period in a dynamic RAM operation. If the refresh period is 1024 refresh cycles for example, stress is put on a corresponding word line by the period of 1024 row address strobe RAS cycles when a row address is sequentially increased. Assuming that the stress time is 48 hours, stress is actually applied to the cell for not 48 hours but 48/1024 hours. Therefore, the stress time applied per cell is not enough. However, if the stress time is increased, the time to complete the chip is also increased.